1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of using scatterometry measurements to determine and control gate electrode profiles, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Typically, integrated circuit devices are comprised of hundreds or millions of transistors formed above a semiconducting substrate. By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate 11.
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modem semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
One illustrative process flow for forming the illustrative transistor 10 will now be described. Initially, the shallow trench isolation regions 18 are formed in the substrate 11 by etching trenches 18A into the substrate 11 and, thereafter, filling the trenches 18A with an appropriate insulating material, e.g., silicon dioxide. Next, a gate insulation layer 16 is formed on the surface 15 of the substrate 11 between the trench isolation regions 18. This gate insulation layer 16 may be comprised of a variety of materials, but it is typically comprised of a thermally grown layer of silicon dioxide. Thereafter, the gate electrode 14 for the transistor 10 is formed by forming a layer of gate electrode material, typically polysilicon, above the gate insulation layer 16, and patterning the layer of gate electrode material using known photolithography and etching techniques to thereby define the gate electrode 14. The sidewalls 14A of the gate electrode 14 tend to flare outwardly a very small amount. Of course, millions of such gate electrodes are being formed across the entire surface of the substrate 11 during this patterning process. The source/drain regions 22 and the sidewall spacers 20 are then formed using a variety of known techniques. Additionally, metal silicide regions (not shown) may be formed above the gate electrode 14 and the source/drain regions 18.
As set forth previously, the critical dimension 12 of the gate electrode 14 is very important in that it, to a great extent, affects many performance characteristics of the completed transistors, e.g., switching speed, leakage currents, etc. FIGS. 2A-2B depict illustrative profiles of gate electrodes 14 for purposes of explanation. The gate electrode 14 in FIGS. 2A depicts a condition referred to as undercutting (region 13A) while the profile in FIG. 2B depicts a condition referred to as flaring or footing (region 13B). The extent of undercutting and footing depicted in FIGS. 2A and 2B, respectively, are exaggerated for purposes of explanation. These problems typically result from the use of a two-step etching process to pattern the gate electrode 14. That is, an initial anisotropic etching process is typically performed to etch through approximately 70-80% of the thickness of the gate electrode layer (a so-called main etch), and a second isotropic etch process is used to complete the etching of the gate electrode layer (a so-called soft landing etch). Such a two-step etching process is performed in an effort to insure that the underlying gate insulation layer 16 is not damaged.
Both undercutting and footing can be problematic in modem integrated circuit devices for a number of reasons. For example, transistors with gate electrodes 14 that exhibit undercutting tend to have a smaller cross-sectional area as compared to an ideal target cross-sectional area and, thus, tend to exhibit larger leakage currents. On the other hand, transistors with gate electrodes 14 that exhibit footing tend to have a larger cross-sectional area than anticipated, and such transistors tend to operate at slower than anticipated speeds.
Typically, after the gate electrode structures 14 are formed, a scanning electron microscope (SEM) may be employed to obtain information about the critical dimensions 12 of the gate electrode structure 14. However, due to the close proximity of the millions of gate electrode structures 14, and the inherent nature of the SEM, the data obtained by the SEM does not reveal the condition of the gate electrode 14 in the area adjacent the gate insulation layer 16. That is, due to excessive noise and interference, the SEM can only be used to see down to about the mid-thickness point 17 of the gate electrode 14. Thus, the profile of the gate electrode 14 adjacent the gate insulation layer 16 cannot readily be examined using an SEM. Typically, one or more production or test wafers that are representative of one or more lots of wafers are eventually cross-sectioned and analyzed to detect the existence of under cutting or footing problems. However, it takes days or weeks to generate results from such destructive testing techniques. During this time, additional gate structures 14 may be being manufactured on additional wafers with undesirable undercutting and footing characteristics. Moreover, the results of such destructive testing techniques are not provided in sufficient time to provide meaningful and relatively rapid feedback to allow more precise control of the processing parameters used to form the gate electrode structures 14.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to a method of using scatterometry measurements to determine and control gate electrode profiles. In one illustrative embodiment, the method comprises providing a library of optical characteristic traces, each of which correspond to a grating structure comprised of a plurality of gate electrode structures having a known profile, providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of gate electrode structures having an unknown profile, and illuminating the grating structure formed above the substrate. The method further comprises measuring light reflected off of the grating structure to generate an optical characteristic trace for the formed grating structure and determining a profile of the gate electrode structures comprising the formed grating structure by correlating the generated optical characteristic trace to an optical characteristic trace from the library. In a further embodiment, the method comprises modifying at least one parameter of at least one etching process used to form gate electrode structures on a subsequently processed substrate based upon the determined profile of the gate electrode structures comprising the formed grating structure. In yet a further embodiment, the library is comprised of a first plurality of traces corresponding to a grating structure comprised of gate electrode structures having a profile that exhibits undercutting, and a second plurality of traces corresponding to a grating structure comprised of gate electrode structures having a profile that exhibits footing.
In another aspect, the present invention is directed to a method whereby a generated trace of a grating structure comprised of a plurality of gate electrode structures having an unknown profile is compared to a target trace established for a grating structure comprised of gate electrode structures having an acceptable profile. In one illustrative embodiment, the method comprises providing a library comprised of at least one optical characteristic trace, one of which is a target trace that corresponds to a grating structure comprised of a plurality of gate electrode structures having a known target profile, and providing a substrate having at least one grating structure formed thereabove, the formed grating structure comprised of a plurality of gate electrode structures having an unknown profile. The method further comprises illuminating the grating structure formed above the substrate, measuring light reflected off of the grating structure to generate an optical characteristic trace for the formed grating structure, and comparing the generated optical characteristic trace to the target trace. In a further embodiment, the method further comprises determining, based upon the comparison of the generated optical characteristic trace and the target trace, at least one parameter of at least one etching process used to form gate electrode structures on a subsequently processed substrate.